1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for delaying data writes to a data cache.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. These multiple agents may make large numbers of requests to memory, and as the number of these requests increases, the power consumption of the device increases, which limits the battery life of the device. One approach for reducing power consumption is to try to reduce the number of times that off-chip memory is accessed by caching data in or near the requesting agent.
Conventional caches are typically coupled to or nearby an agent and store data that is frequently accessed by the agent to reduce latency. For example, processor cores often include caches and may also be coupled to additional external caches in a cache memory hierarchy. For example, in a system with a two-level cache hierarchy, a level two (L2) cache may be inclusive of one or more write-back level one (L1) caches. Typically, a request from a core that misses in the L2 cache will bring the corresponding cache line from memory into the L2 cache data array, update the state of the L2 cache, and then update the L1 cache. If the core subsequently dirties the line, the L2 data array will be updated yet again when the line is evicted from the core. Therefore, the first write to the L2 data array was unnecessary and contributes to increased power consumption.